The present invention relates to semiconductor storage devices, and in particular, to a semiconductor storage device having a nonvolatile memory.
In recent years, nonvolatile semiconductor storage devices have made remarkable progress, and their storage capacities are rapidly increasing.
For the purpose of increasing the storage capacity through an identical manufacturing process, it is required to reduce the area per memory cell. Then, there is a device for reducing the number of contacts of bit lines with metal wiring lines by connecting a number of (e.g., 64) memory cells to a series of extension bit lines.
On the other hand, as a method for discriminating between "0" and "1" of information retained in the memory cells by detecting the level of the threshold voltage of each transistor constituting the memory cell, a current sensing method and a voltage sensing method exist.
According to the current sensing method, when selecting a memory cell, the current sensing is effected by deciding whether or not a current flows through the transistor constituting the selected memory cell. According to the voltage sensing method, a bit line is pre-charged, and after a memory cell connected to this bit line is selected, the voltage sensing is effected after waiting a sufficient time for the reduction of the voltage at the bit line to a reference voltage of a sense amplifier or a lower voltage.
The above voltage sensing method will be described below with reference to FIGS. 19 and 20.
Referring to FIG. 19, in a reading stage, firstly the level of a pre-charge signal .phi.pre supplied to the gate electrodes of transistors 1 and 2 and the level of a cutoff signal .phi.cut supplied to the gate electrodes of transistors 3 and 4 are set to Vcc. Then, the transistors 1, 2, 3 and 4 are turned on, so that input nodes 8 and 9 of inverters 6 and 7 constituting a sense amplifier 5 are charged with a pre-charge voltage Vpre via data lines 11 and 12 and the transistors 3 and 4.
Then, the pre-charge signal .phi.pre is reduced to the GND level at a time point to (see FIG. 20) thereby turning off the transistors 1 and 2, and thereafter one memory cell is selected by a row decoder 14 and a column decoder 15 according to an address signal from an address bus 13 at a time point t1, so that the bit line and data line 11 corresponding to this selected memory cell are connected to each other. When a current flows through the above bit line via the selected memory cell, (i.e., when the retained information is "0"), the input node 8 and the data line 11 are discharged, so that their voltages are reduced from the pre-charge voltage Vpre.
Subsequently, a transistor 18 is turned on by setting the level of a reference signal .phi.ref supplied to the gate electrode of the transistor 18 to Vcc at a time point t2, thereby setting the voltages at the data line 12 and the input node 9 to a reference voltage Vref. When the electric potential at the input node 8 is reduced from the pre-charge voltage Vpre to a level that is lower than the reference voltage Vref by a sensing sensitivity (a voltage with which the sense amplifier 5 starts its sensing operation) .DELTA.V or a lower level, a potential difference .DELTA.V corresponding to the sensing sensitivity is generated between the input node 8 and the input node 9.
At the time point t3, the cutoff signal .phi.cut supplied to the gate electrode of the transistor 3 is reduced to the GND level, thereby disconnecting the sense amplifier 5 from a memory cell array 10. Then, the level of a sense amplifier drive signal .phi.se# is set to GND at a time point t4 thereby turning on a transistor 16, and the level of a sense amplifier drive signal .phi.se is set to Vcc at a time point t5 thereby turning on a transistor 17, so that the sense amplifier 5 is driven to amplify the potential difference between the input nodes 8 and 9.
The thus amplified potential difference between the input nodes 8 and 9 is read from output terminals by turning on the transistors 19 and 20.
As a method for increasing the storage capacity by the same manufacturing process as the prior art, there is a method for increasing the number of bits of information which can be stored in one memory cell (providing so-called the multi-valued construction). In a flash memory or the like, the multi-valued construction is provided by controlling the threshold voltage of each transistor constituting the memory cell. In such a case, a sensing operation is required to be executed two or more times for the purpose of reading the information retained in the memory cell.
The read operation will be described below taking the case where four values (two bits in terms of information quantity) are stored into one memory cell as an example. FIG. 21 is a block diagram of the sense amplifier and its peripherals in the nonvolatile semiconductor storage device in which four values are stored into one memory cell. In this case, three types of reference voltages VrefH, VrefM and VrefL are used for executing the operation of sensing the four values.
First, for example, information stored in a memory cell CELLO is sensed with the reference voltage VrefM by a first sense amplifier SA1. Subsequently, a voltage at an input node SN0 is supplied to the gate of a transistor Tr2 by a transistor Tr3 which is turned on and off upon the application of a sensing result transfer signal REFon thereto. Similarly, a voltage at an input node SN1 is supplied to the gate of a transistor Tr1 by a transistor Tr4 which is turned on and off upon the application of the sensing result transfer signal REFon thereto. Thus, the reference voltage of a second sense amplifier SA2 is set to either one of VrefH and VrefL according to the voltages at the input node SN0 and the input node SN1 (i.e., according to the sensing result of the first sense amplifier SA1).
In the case of the nonvolatile semiconductor storage device shown in FIG. 21, it is assumed that the information is "1" when a current flows through a bit line BL via the memory cell CELLO and the information is "0" when no current flows, contrary to the case of the nonvolatile semiconductor storage device shown in FIG. 19.
The sensing operation of the nonvolatile semiconductor storage device shown in FIG. 21 will be described in concrete below.
FIG. 22 is a timing chart showing a sensing operation in the case where the information retained in the memory cell CELLO is "00" or "01". Further, FIG. 23 is a timing chart showing a sensing operation in the case where the information retained in the memory cell CELLO is "10" or "11".
Referring to FIG. 22, the information retained in the memory cell CELLO is "00" or "01", and therefore, the input node SN0 is not discharged to a voltage below the reference voltage VrefM. Therefore, the voltage at the input node SN0 is increased to Vcc, while the voltage at the input node SN1 is reduced to GND. Therefore, when the sensing result transfer signal REFon becomes Vcc, the transistor Tr2 is turned on and the reference voltage of the second sense amplifier SA2 becomes VrefH which is higher by 2.DELTA.V than VrefM. When the information retained in the memory cell CELLO is "01", the discharge voltage at an input node SN2 becomes lower than the reference voltage VrefH, and therefore, the voltage at the input node SN2 is reduced to GND. In contrast to this, when the information is "00", the voltage at the input node SN2 is not discharged, and therefore, the reference voltage does not become lower than the reference voltage VrefH. Therefore, the voltage at the input node SN2 is increased to Vcc.
That is, according to the voltages at the input nodes SN0 and SN2, the information retained in the memory cell CELLO is decided as follows:
input node SN0=Vcc, input node SN2=Vcc PA1 input node SN0=Vcc, input node SN2=GND PA1 input node SN0=GND, input node SN2=Vcc PA1 input node SN0=GND, input node SN2=GND PA1 a memory cell array having a plurality of nonvolatile memory cells, bit lines and word lines; PA1 a row decoding circuit which selects the word line of the memory cell array; PA1 a column decoding circuit which selects the bit line of the memory cell array; PA1 a data line connected to the bit line selected by the column decoding circuit; PA1 a sense amplifier which has a first input terminal and a second input terminal connected to the data line and amplifies a voltage difference between the first input terminal and the second input terminal; PA1 a pre-charging circuit which pre-charges the first and second input terminals with a specified voltage; PA1 a switching circuit which effects connection and disconnection between the data line and the second input terminal; and PA1 a voltage setting circuit which boosts or deboosts the voltage at the second input terminal by a specified voltage, thereby setting a sensing level of the sense amplifier. PA1 a row decoding circuit which selects the word line of the memory cell array; PA1 a column decoding circuit which selects the bit line of the memory cell array; PA1 a data line connected to the first input terminal of the sense amplifier and the bit line selected by the column decoding circuit; PA1 a switching circuit which effects connection and disconnection between the first input terminal of the sense amplifier and the data line of the first input terminal side; PA1 a voltage setting circuit which boosts or deboosts the voltage at the first input terminal by the specified voltage, thereby setting the sensing level of the sense amplifier; and PA1 a selecting circuit which selectively operates either one of the voltage setting circuit for boosting or deboosting the voltage at the first input terminal and the voltage setting circuit for boosting or deboosting the voltage at the second input terminal. PA1 a memory cell array having a plurality of nonvolatile memory cells, bit lines and word lines; PA1 a row decoding circuit which selects the word line of the memory cell array; PA1 a column decoding circuit which selects the bit line of the memory cell array; PA1 at least two first and second sense amplifiers which have a first input terminal and a second input terminal connected to the bit line and amplify a voltage difference between the first input terminal and the second input terminal; PA1 a switching circuit which effects connection and disconnection between the bit line selected by the column decoding circuit and the second input terminals of the first and second sense amplifiers; PA1 a pre-charging circuit which pre-charges the first and second input terminals of the first and second sense amplifiers with a specified voltage; PA1 a first voltage setting circuit which boosts or deboosts the voltages at the second input terminals of the first and second sense amplifiers by a specified voltage, thereby setting the voltage at the second input terminals; PA1 a second voltage setting circuit which boosts or deboosts the voltage at the first input terminal of the second sense amplifier by a specified voltage, thereby setting a sensing level of the second sense amplifier; PA1 a third voltage setting circuit which boosts or deboosts the voltage at the second input terminal of the second sense amplifier by a specified voltage, thereby setting the sensing level of the second sense amplifier; and PA1 a selecting circuit which selectively operates either one of the second voltage setting circuit and the third voltage setting circuit based on the voltages at the first input terminal and the second input terminal of the first sense amplifier. PA1 a memory cell array having a plurality of nonvolatile memory cells, bit lines and word lines; PA1 a row decoding circuit which selects the word line of the memory cell array; PA1 a column decoding circuit which selects the bit line of the memory cell array; PA1 at least two first and second sense amplifiers which have a first input terminal and a second input terminal connected to the bit line and amplify a voltage difference between the first input terminal and the second input terminal; PA1 a switching circuit which effects connection and disconnection between the bit line selected by the column decoding circuit and the second input terminals of the first and second sense amplifiers; PA1 a pre-charging circuit which pre-charges the first and second input terminals of the first and second sense amplifiers with a specified voltage; PA1 a voltage setting circuit which boosts or deboosts the voltages at the second input terminals of the first and second sense amplifiers by a specified voltage, thereby setting the voltage at the second input terminal; PA1 a first capacitive element provided across the first input terminal of the first sense amplifier and the second input terminal of the second sense amplifier; and PA1 a second capacitive element provided across the second input terminal of the first sense amplifier and the first input terminal of the second sense amplifier.
.fwdarw.retained information="00" PA2 .fwdarw.retained information="01" PA2 .fwdarw.retained information="10" PA2 .fwdarw.retained information="11"
On the other hand, in FIG. 23, the information retained in the memory cell CELLO is "10" or "11", and therefore, the input node SN0 is discharged to a voltage which is not higher than the reference voltage VrefM. Therefore, the voltage at the input node SN0 is reduced to GND, while the voltage at the input node SN1 is increased to Vcc. Therefore, when the sensing result transfer signal REFon becomes Vcc, the transistor Tr1 is turned on and the reference voltage at the second sense amplifier SA2 becomes VrefL which is lower by 2.DELTA.V than VrefM. When the information retained in the memory cell CELLO is "11", the discharge voltage at the input node SN2 becomes lower than the reference voltage VrefL, and therefore, the voltage at the input node SN2 is reduced to GND. In contrast to this, in the case where the information is "10", the discharge voltage at the input node SN2 does not become lower than the reference voltage VrefL. Therefore, the voltage at the input node SN2 is increased to Vcc.
Therefore, according to the voltages at the input nodes SN0 and SN2, the information retained in the memory cell CELLO is decided as follows.
That is, in the nonvolatile semiconductor storage device having the above construction, it is required to execute the sensing operation (log.sub.2 n) times with (n-1) types of reference voltages for the purpose of reading the information of n values from the memory cells of the memory cell array.
However, the method for discriminating between "0" and "1" of the information retained in the memory cell of the nonvolatile semiconductor storage device shown in FIG. 19 has the following problems.
First, in the case of the current sensing method, diffused resistance (e.g., 10 k.OMEGA.) of the bit line becomes substantially equal to the On-state resistance of the transistor constituting each memory cell, and this causes the problem that it is difficult to secure a sufficient current value (e.g., 100 .mu.A) for executing the current sensing.
Furthermore, in the case of the voltage sensing method, the pre-charge voltage Vpre is set higher than the reference voltage Vref, and therefore, the voltage Vpre on the bit line is reduced to the reference voltage Vref of the sense amplifier 5 (at a time point tx) and further reduced to a level lower than the reference level Vref by not smaller than the sensing sensitivity .DELTA.V when discharging the electric charges accumulated in the capacitance (e.g., 4 pF) of the bit line. It is required to wait a time (from time point t1 to time point t3) for this reduction of the voltage. This leads to the problem that too much time (e.g., 250 nsec) is required for the discharging.
In this case, the discharging time can be reduced if the pre-charge voltage Vpre is put closer to the reference voltage Vref. However, since a large fluctuation in voltage has been generated by the prior art voltage generating circuit, it is difficult to set the pre-charge voltage Vpre with an accuracy of about 0.1 V corresponding to the sensing sensitivity .DELTA.V. Therefore, it is impossible to put the pre-charge voltage Vpre closer to the reference voltage Vref with a difference of the sensing sensitivity .DELTA.V provided, and therefore, this measure scarcely contributes to the reduction of the discharging time.
Furthermore, for the purpose of reading the multi-valued information retained in the memory cells of the nonvolatile semiconductor storage device shown in FIG. 21, it is required to execute the sensing operation many times with various kinds of reference voltages provided as stated above. Therefore, when reading the multi-valued information retained in the memory cells of the prior art nonvolatile semiconductor storage device, there is the problem of an increase in number of circuits by the reference voltage generating circuits.
Furthermore, as shown in FIGS. 22 and 23, there is required a time of 20 nsec for a decision time of t4 to t5 for deciding which one of the reference voltages VrefL and VrefH is to be selected, and a time of 10 nsec is required for a time of t5 to t6 for the stabilization of the selected reference voltage. Therefore, a time of 55 nsec is required for a time of t2 to t7 from the disconnection of the input nodes SN0 and SN2 from the bit line BL0 to the completion of the sensing operation of the second sense amplifier SA2, and this causes the problem of a delay in the access time.